38 search results - page 4 / 8 » Serial-link bus: a low-power on-chip bus architecture |
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. ...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access and data transfer. Thus, buses should be d...
ISCAS
2002
IEEE
14 years 9 days ago
2002
IEEE
Pre-designed configurable platforms, possessing microprocessors, memories, and numerous peripherals on a single chip, are increasing in popularity in embedded system design. Platf...
SLIP
2006
ACM
14 years 1 months ago
2006
ACM
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
BWCCA
2010
13 years 2 months ago
2010
Network-on-Chip (NoC) architectures provide a good way of realizing efficient interconnections and largely alleviate the limitations of bus-based solutions. NoC has emerged as a so...