13 search results - page 1 / 3 » Signal Integrity: Fault Modeling and Testing in High-Speed S... |
ET
2002
13 years 9 months ago
2002
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay viol...
GLVLSI
2002
IEEE
14 years 2 months ago
2002
IEEE
We present a novel test scheduling algorithm for embedded corebased SoC’s. Given a system integrated with a set of cores and a set of test resources, we select a test for each c...
DDECS
2007
IEEE
14 years 4 months ago
2007
IEEE
Abstract: High speed DRAMs today suffer from an increased sensitivity to interference and noise problems. Signal integrity issues, caused by bit line and word line coupling, result...
DAC
2006
ACM
13 years 11 months ago
2006
ACM
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
ICCAD
2000
IEEE
14 years 2 months ago
2000
IEEE
In this paper, we present a novel approach to use test stimuli generated by digital components of a mixed-signal circuit for testing its analog components. A wavelet transform is ...