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VLSID
2002
IEEE
151views VLSI» more  VLSID 2002»
14 years 9 months ago
Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems
Among the many techniques for system-level power management, it is not currently possible to guarantee timing constraints and have a comprehensive system model at the same time. S...
Dexin Li, Pai H. Chou, Nader Bagherzadeh
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 5 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
DATE
2010
IEEE
160views Hardware» more  DATE 2010»
14 years 1 months ago
Soft error-aware design optimization of low power and time-constrained embedded systems
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
Rishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu...
SPAA
2010
ACM
13 years 9 months ago
Scheduling to minimize power consumption using submodular functions
We develop logarithmic approximation algorithms for extremely general formulations of multiprocessor multiinterval offline task scheduling to minimize power usage. Here each proce...
Erik D. Demaine, Morteza Zadimoghaddam
ICCAD
2001
IEEE
201views Hardware» more  ICCAD 2001»
14 years 5 months ago
An Integrated Data Path Optimization for Low Power Based on Network Flow Method
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu