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DATE
2004
IEEE
120views Hardware» more  DATE 2004»
14 years 25 days ago
Pattern Selection for Testing of Deep Sub-Micron Timing Defects
Due to process variations in deep sub-micron (DSM) technologies, the effects of timing defects are difficult to capture. This paper presents a novel coverage metric for estimating...
Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
14 years 3 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
14 years 2 months ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
TPDS
2010
164views more  TPDS 2010»
13 years 3 months ago
Energy-Efficient Wake-Up Scheduling for Data Collection and Aggregation
The basic operation in such a network is the systematic gathering (with or without in-network aggregation) and transmitting of sensed data to a base station for further processing....
Yanwei Wu, Xiang-Yang Li, Yunhao Liu, Wei Lou
ASAP
2006
IEEE
142views Hardware» more  ASAP 2006»
13 years 11 months ago
NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm
In this paper, a routing model for minimizing hot spots in the network on chip (NOC) is presented. The model makes use of AntNet routing algorithm which is based on Ant colony. Us...
Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kus...