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» Simulation based deadlock analysis for system level designs
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HYBRID
1994
Springer
13 years 11 months ago
DEVS Framework for Modelling, Simulation, Analysis, and Design of Hybrid Systems
We make the case that Discrete Event System Speci cation DEVS is a universal formalismfor discrete event dynamical systems DEDS. DEVS o ers an expressive framework for modelling, ...
Bernard P. Zeigler, Hae Sang Song, Tag Gon Kim, He...
ISSS
2002
IEEE
144views Hardware» more  ISSS 2002»
14 years 12 days ago
A Visual Approach to Validating System Level Designs
This paper proposes a simulation-based methodology for validation of a system under design in an early phase of development. The key element of this approach is the visual speci...
Jürgen Ruf, Thomas Kropf, Jochen Klose
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
14 years 1 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
DATE
2006
IEEE
135views Hardware» more  DATE 2006»
14 years 1 months ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
LCTRTS
1998
Springer
13 years 11 months ago
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
Thomas Lundqvist, Per Stenström