In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reductio...
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient ...
Georges G. E. Gielen, Trent McConaghy, Tom Eeckela...
Abstract— Numerous machine-learning-based test methodologies have been proposed in recent years as a fast alternative to the standard functional testing of mixed-signal/RF integr...
The traditionally wired interfaces of many electronic systems are in many applications being replaced by wireless interfaces. Testing of electronic systems (both integrated circui...
Erik Jan Marinissen, Dae Young Lee, John P. Hayes,...
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
Pawan Kulshreshtha, Robert Palermo, Mohammad Morta...