154 search results - page 5 / 31 » Simulation of Bulk Flow and High Speed Operations |
VLSI
2010
Springer
13 years 2 months ago
2010
Springer
A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation...
PATMOS
2004
Springer
14 years 1 months ago
2004
Springer
The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...
ISLPED
1996
ACM
13 years 11 months ago
1996
ACM
The power versus frequency performance of a micropipelined conventional CMOS logic family is compared with that of three similarly pipelined energy-recovering logic families. Usin...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
: This paper presents a self-calibration method for designing high speed pipeline ADCs. Unlike all existing calibration algorithms, the proposed calibration does not insert any tes...
ISNN
2007
Springer
14 years 1 months ago
2007
Springer
This paper presents a new approach to speed up the operation of time delay neural networks for fast code detection. The entire data are collected together in a long vector and then...