1304 search results - page 208 / 261 » Simulation of Soliton Circuits |
ISPD
2005
ACM
14 years 2 months ago
2005
ACM
In this paper, the problem of bus-driven floorplanning is addressed. Given a set of blocks and the bus specification (the width of each bus and the blocks that the bus need to g...
ISCAS
2003
IEEE
14 years 2 months ago
2003
IEEE
This paper investigates the feasibility of the application of class E RF power amplifiers in UMTS. A typical class E circuit has been designed and simulated, in conjunction with ...
ITC
2000
IEEE
14 years 1 months ago
2000
IEEE
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...
ASPDAC
1999
ACM
14 years 1 months ago
1999
ACM
We propose a new technique called node sampling to speed up the probability-based power estimation methods. It samples and processes only a small portion of total nodes to estimat...
ASPDAC
2007
ACM
14 years 26 days ago
2007
ACM
- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...