1304 search results - page 29 / 261 » Simulation of Soliton Circuits |
ISQED
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit ar...
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
The architectural study of wireless communication systems typically requires simulations with high-level models for different analog and RF blocks. Among these blocks, frequency-t...
ICCAD
1999
IEEE
14 years 1 months ago
1999
IEEE
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low ove...
ASPDAC
2005
ACM
14 years 2 months ago
2005
ACM
-We propose a method involvingselectivesignalgating to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current ...