78 search results - page 5 / 16 » Simultaneous buffer and wire sizing for performance and powe... |
ISPD
2000
ACM
13 years 11 months ago
2000
ACM
In this paper, we present an algorithm for delay minimization of interconnect trees by simultaneous buffer insertion/sizing and wire sizing. The algorithm integrates the quadratic...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
ISCA
2008
IEEE
13 years 7 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity O(n2 ), where n is the number of possible buffer positions. We present a new a...
ISLPED
2005
ACM
14 years 29 days ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...