Sciweavers

78 search results - page 8 / 16
» Simultaneous buffer and wire sizing for performance and powe...
Sort
View
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
14 years 4 months ago
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction
Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduc...
Feng Gao, John P. Hayes
ICCAD
2001
IEEE
100views Hardware» more  ICCAD 2001»
14 years 4 months ago
Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. T...
Kaustav Banerjee, Amit Mehrotra
ASPDAC
2006
ACM
110views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Switching-activity driven gate sizing and Vth assignment for low power design
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang
ICCAD
2008
IEEE
116views Hardware» more  ICCAD 2008»
14 years 4 months ago
Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example
—Connecting system-level performance models with circuit information has been a long-standing problem in analog/mixed-signal front-ends, like radios and high-speed links. High-sp...
Ranko Sredojevic, Vladimir Stojanovic
ASAP
2006
IEEE
134views Hardware» more  ASAP 2006»
13 years 9 months ago
Buffer and register allocation for memory space optimization
In today's embedded systems, memory hierarchy is rapidly becoming a major factor in terms of power, performance and area. This is especially true for embedded multimedia appl...
Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha...