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179
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TVLSI
2008
187views more  TVLSI 2008»
15 years 3 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...
131
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DAC
2001
ACM
16 years 4 months ago
Latency-Driven Design of Multi-Purpose Systems-On-Chip
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
Seapahn Meguerdichian, Milenko Drinic, Darko Kirov...
134
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ICCAD
2000
IEEE
109views Hardware» more  ICCAD 2000»
15 years 8 months ago
Latency-Guided On-Chip Bus Network Design
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
Milenko Drinic, Darko Kirovski, Seapahn Meguerdich...
117
Voted
ICCD
2004
IEEE
135views Hardware» more  ICCD 2004»
16 years 12 days ago
Design Methodologies and Architecture Solutions for High-Performance Interconnects
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...
Davide Pandini, Cristiano Forzan, Livio Baldi
148
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ACMIDC
2009
15 years 7 months ago
Designing intergenerational mobile storytelling
Informal educational experiences with grandparents and other older adults can be an important component of childrens education, especially in circumstances where high quality educ...
Allison Druin, Benjamin B. Bederson, Alexander J. ...