FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
Starting from a model of the within-die systematic variations using principal components analysis, a model is proposed for estimation of the parametric yield, and is then applied ...
This paper presents a new perspective for the design of indoor navigation support. In contrast to technology oriented approaches coming from Context Awareness research, we argue f...
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden a...
Michael Hutton, Richard Yuan, Jay Schleicher, Greg...