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DAC
2008
ACM
14 years 10 months ago
Enhancing timing-driven FPGA placement for pipelined netlists
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
Kenneth Eguro, Scott Hauck
DAC
2004
ACM
14 years 10 months ago
Post-layout logic optimization of domino circuits
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
Aiqun Cao, Cheng-Kok Koh
DAC
2004
ACM
14 years 10 months ago
Statistical timing analysis based on a timing yield model
Starting from a model of the within-die systematic variations using principal components analysis, a model is proposed for estimation of the parametric yield, and is then applied ...
Farid N. Najm, Noel Menezes
CHI
2009
ACM
14 years 10 months ago
Towards human-centered support for indoor navigation
This paper presents a new perspective for the design of indoor navigation support. In contrast to technology oriented approaches coming from Context Awareness research, we argue f...
Leonardo Ramirez, Sebastian Denef, Tobias Dyrks
DATE
2006
IEEE
96views Hardware» more  DATE 2006»
14 years 3 months ago
A methodology for FPGA to structured-ASIC synthesis and verification
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden a...
Michael Hutton, Richard Yuan, Jay Schleicher, Greg...