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ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
15 years 9 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
15 years 9 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
MFCS
2005
Springer
15 years 9 months ago
Nondeterministic Graph Searching: From Pathwidth to Treewidth
Abstract. We introduce nondeterministic graph searching with a controlled amount of nondeterminism and show how this new tool can be used in algorithm design and combinatorial anal...
Fedor V. Fomin, Pierre Fraigniaud, Nicolas Nisse
ISLPED
2004
ACM
169views Hardware» more  ISLPED 2004»
15 years 9 months ago
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
Deming Chen, Jason Cong
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
15 years 9 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen