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DATE
2006
IEEE
109views Hardware» more  DATE 2006»
14 years 3 months ago
A secure scan design methodology
It has been proven that scan path is a potent hazard for secure chips. Scan based attacks have been recently demonstrated against DES or AES and several solutions have been presen...
David Hély, Frédéric Bancel, ...
ISSRE
2006
IEEE
14 years 3 months ago
A Systematic Approach to Generate Inputs to Test UML Design Models
Practical model validation techniques are needed for model driven development (MDD) techniques to succeed. This paper presents an approach to generating inputs to test UML design ...
Trung T. Dinh-Trong, Sudipto Ghosh, Robert B. Fran...
ASPDAC
1995
ACM
130views Hardware» more  ASPDAC 1995»
14 years 21 days ago
Design for testability using register-transfer level partial scan selection
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...
Akira Motohara, Sadami Takeoka, Toshinori Hosokawa...
TCAD
1998
83views more  TCAD 1998»
13 years 8 months ago
Telescopic units: a new paradigm for performance optimization of VLSI designs
—This paper introduces a novel optimization paradigm for increasing the throughput of digital systems. The basic idea consists of transforming fixed-latency units into variable-...
Luca Benini, Enrico Macii, Massimo Poncino, Giovan...
EWSN
2004
Springer
14 years 8 months ago
Design of a Secure Distributed Service Directory for Wireless Sensornetworks
Sensor networks consist of a potentially huge number of very small and resource limited self-organizing devices. This paper presents the design of a general distributed service dir...
Erik-Oliver Blaß, Hans-Joachim Hof, Martina ...