71 search results - page 7 / 15 » Snug set-associative caches: reducing leakage power while im... |
ISLPED
2003
ACM
14 years 28 days ago
2003
ACM
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...
JEC
2006
13 years 7 months ago
2006
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
Main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a PowerAw...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...