155 search results - page 14 / 31 » Soft delay error analysis in logic circuits |
DFT
2008
IEEE
14 years 2 months ago
2008
IEEE
With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based ...
ISQED
2008
IEEE
14 years 2 months ago
2008
IEEE
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that opera...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...
ATS
2000
IEEE
14 years 3 days ago
2000
IEEE
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...