155 search results - page 24 / 31 » Soft delay error analysis in logic circuits |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
This paper presents analysis methods for energy estimation in RC trees driven by time-varying voltage sources, e.g., buffers, timevarying power supplies, and resonant clock genera...
DATE
2000
IEEE
14 years 2 days ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
- Advanced process technologies impose more significant challenges especially when manufactured circuits exhibit substantial process variations. Consideration of process variations...
DATE
2010
IEEE
14 years 23 days ago
2010
IEEE
With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred...
VTS
2006
IEEE
14 years 1 months ago
2006
IEEE
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...