155 search results - page 26 / 31 » Soft delay error analysis in logic circuits |
DATE
2002
IEEE
14 years 19 days ago
2002
IEEE
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Trace buffer technology allows tracking the values of a few number of state elements inside a chip within a desired time window, which is used to analyze logic errors during post-s...
TCAD
2002
13 years 7 months ago
2002
We develop a general methodology to analyze crosstalk effects that are likely to cause errors in deep submicron high speed circuits. We focus on crosstalk due to capacitive coupli...