155 search results - page 7 / 31 » Soft delay error analysis in logic circuits |
FPL
2003
Springer
14 years 27 days ago
2003
Springer
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
We analyze the neutron induced soft error rate (SER). An induced error pulse is modeled by two parameters, probability of occurrence and probability density function of the pulse ...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
- This paper performs analysis and design of latches and flip-flops while considering the effect of event upsets caused by energetic particle hits. First it is shown that the conve...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
1 Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit ...