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» Statistical Approach to Networks-on-Chip
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126
Voted
DAC
2008
ACM
16 years 4 months ago
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction man...
Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan
137
Voted
DAC
2008
ACM
16 years 4 months ago
The synthesis of robust polynomial arithmetic with stochastic logic
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
Weikang Qian, Marc D. Riedel
132
Voted
DAC
2001
ACM
16 years 4 months ago
Latency-Driven Design of Multi-Purpose Systems-On-Chip
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
Seapahn Meguerdichian, Milenko Drinic, Darko Kirov...
127
Voted
DAC
2003
ACM
16 years 4 months ago
A scalable software-based self-test methodology for programmable processors
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...
Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit D...
134
Voted
DAC
2005
ACM
16 years 4 months ago
Power emulation: a new paradigm for power estimation
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
Joel Coburn, Srivaths Ravi, Anand Raghunathan