306 search results - page 58 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Most shared memory systems maximize performance by unpredictably resolving memory races. Unpredictable memory races can lead to nondeterminism in parallel programs, which can suff...
BXML
2004
13 years 8 months ago
2004
: ExtraPlanT system is a multi-agent production planning system designed for small factories, which needs to react quickly on market changes. To deal with this requirement, ExtraPl...
PATMOS
2004
Springer
14 years 20 days ago
2004
Springer
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
ASPDAC
2009
ACM
14 years 1 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...