306 search results - page 5 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
DATE
2002
IEEE
14 years 8 days ago
2002
IEEE
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
– The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...