1459 search results - page 14 / 292 » Statistical Modeling for Circuit Simulation |
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
In the last decade, the focus of fault-tolerance methods has tended towards circuit level modifications, such as transistor resizing, and away from expensive system level redunda...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits. Three primary techniques in CONCERT, including fault ordering, state predict...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
— For 65nm and below devices, even after optical proximity correction (OPC), the gate may still be non-rectangular. There are several limited works on the device and circuit char...
DATE
2003
IEEE
14 years 26 days ago
2003
IEEE
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
DATE
2010
IEEE
14 years 20 days ago
2010
IEEE
—This paper presents a modeling method for power distribution networks (PDNs) consisting of multilayered power/ground planes of the PCB/Package. Using our proposed method, multip...