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» Statistical Modeling for Circuit Simulation
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DSN
2005
IEEE
14 years 4 months ago
Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files
Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop er...
Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, ...
ISCAS
2005
IEEE
224views Hardware» more  ISCAS 2005»
14 years 4 months ago
A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter
— A new operation mode using a partially depleted hybrid lateral BJT-CMOS inverter on SOI, named as a new unified-BiCMOS (U-BiCMOS) inverter, is proposed. The scheme utilizes the...
Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga
ISQED
2005
IEEE
140views Hardware» more  ISQED 2005»
14 years 4 months ago
Toward Quality EDA Tools and Tool Flows Through High-Performance Computing
As the scale and complexity of VLSI circuits increase, Electronic Design Automation (EDA) tools become much more sophisticated and are held to increasing standards of quality. New...
Aaron N. Ng, Igor L. Markov
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 4 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
14 years 3 months ago
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis
— Memory is one of the most important components to be optimized in the several phases of the synthesis process. ioral synthesis, a memory is viewed as an abstract construct whic...
Gernot Koch, Taewhan Kim, Reiner Genevriere