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» Statistical gate delay model for Multiple Input Switching
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TVLSI
2008
110views more  TVLSI 2008»
13 years 7 months ago
Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits
Abstract--The quantum-dot cellular automata (QCA) model offers a novel nano-domain computing architecture by mapping the intended logic onto the lowest energy configuration of a co...
Sanjukta Bhanja, Sudeep Sarkar
DATE
2008
IEEE
125views Hardware» more  DATE 2008»
14 years 2 months ago
Current source based standard cell model for accurate signal integrity and timing analysis
— The inductance and coupling effects in interconnects and non-linear receiver loads has resulted in complex input signals and output loads for gates in the modern deep submicron...
Amit Goel, Sarma B. K. Vrudhula
VLSID
2002
IEEE
129views VLSI» more  VLSID 2002»
14 years 8 months ago
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis
In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on an...
Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylves...
ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
14 years 29 days ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov
VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
14 years 8 months ago
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos