246 search results - page 26 / 50 » Statistical gate sizing for timing yield optimization |
CODES
2010
IEEE
13 years 5 months ago
2010
IEEE
The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of...
DRR
2008
13 years 9 months ago
2008
Adaptive binarization is an important first step in many document analysis and OCR processes. This paper describes a fast adaptive binarization algorithm that yields the same qual...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Negative Bias Temperature Instability (NBTI) is a significant reliability concern for nanoscale CMOS circuits. Its effects on circuit timing can be especially pronounced for ci...
FCCM
2008
IEEE
14 years 2 months ago
2008
IEEE
Power reduction is becoming more important as circuit size increases. This paper presents a tool called PowerCutter which employs accuracy-guaranteed word-length optimization to r...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...