2286 search results - page 33 / 458 » Statistical timing analysis based on a timing yield model |
144
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ICCAD
2009
IEEE
15 years 2 months ago
2009
IEEE
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
133
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ICCAD
2001
IEEE
16 years 1 months ago
2001
IEEE
We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simu...
150
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WCET
2003
15 years 5 months ago
2003
Worst-Case Execution Time (WCET) analysis means to compute a safe upper bound to the execution time of a piece of code. Parametric WCET analysis yields symbolic upper bounds: expr...
119
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DAC
2008
ACM
16 years 5 months ago
2008
ACM
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
136
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RTSS
1998
IEEE
15 years 8 months ago
1998
IEEE
We propose a unifying method for analysis of scheduling problems in real-time systems. The method is based on ACSR-VP, a real-time process algebra with value-passing capabilities....