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FPL
2004
Springer
93views Hardware» more  FPL 2004»
14 years 3 months ago
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays
This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPG...
Steven J. E. Wilton, Su-Shin Ang, Wayne Luk
DFT
2003
IEEE
98views VLSI» more  DFT 2003»
14 years 3 months ago
Constrained ATPG for Broadside Transition Testing
In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally...
Xiao Liu, Michael S. Hsiao
ITC
2003
IEEE
214views Hardware» more  ITC 2003»
14 years 3 months ago
ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume
This paper presents an approach for reducing the test data volume that has to be stored in ATE vector memory for IC manufacturing testing. We exploit the capabilities of present A...
Harald P. E. Vranken, Friedrich Hapke, Soenke Rogg...
DAC
2003
ACM
14 years 3 months ago
Test generation for designs with multiple clocks
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
Xijiang Lin, Rob Thompson
DFT
2002
IEEE
103views VLSI» more  DFT 2002»
14 years 3 months ago
Input Ordering in Concurrent Checkers to Reduce Power Consumption
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
Kartik Mohanram, Nur A. Touba