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ICCAD
2006
IEEE
100views Hardware» more  ICCAD 2006»
14 years 6 months ago
Faster, parametric trajectory-based macromodels via localized linear reductions
— Trajectory-based methods offer an attractive methodology for automated, on-demand generation of macromodels for custom circuits. These models are generated by sampling the stat...
Saurabh K. Tiwary, Rob A. Rutenbar
DATE
2005
IEEE
112views Hardware» more  DATE 2005»
14 years 3 months ago
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinab...
APCCAS
2002
IEEE
157views Hardware» more  APCCAS 2002»
14 years 2 months ago
Multiplier energy reduction through bypassing of partial products
Designof portablebattery operatedmultimediadevices requires energy-ecient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital mul...
Jun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue
DFT
2003
IEEE
79views VLSI» more  DFT 2003»
14 years 3 months ago
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits
A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic cir...
Kartik Mohanram, Nur A. Touba
DAC
2003
ACM
14 years 10 months ago
A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEM
In this paper we propose a method for generating reduced models for a class of nonlinear dynamical systems, based on truncated balanced realization (TBR) algorithm and a recently ...
Dmitry Vasilyev, Michal Rewienski, Jacob White