Sciweavers

871 search results - page 19 / 175
» Streaming Reduction Circuit
Sort
View
FPGA
1998
ACM
153views FPGA» more  FPGA 1998»
14 years 2 months ago
SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays
It has become clear that large embedded con gurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage...
Steven J. E. Wilton
ISLPED
1997
ACM
94views Hardware» more  ISLPED 1997»
14 years 1 months ago
A gate resizing technique for high reduction in power consumption
With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this paper, we propose a post
Patrick Girard, Christian Landrault, Serge Pravoss...
DAC
2003
ACM
14 years 10 months ago
A transformation based algorithm for reversible logic synthesis
A digital combinational logic circuit is reversible if it maps each input pattern to a unique output pattern. Such circuits are of interest in quantum computing, optical computing...
D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
ISLPED
1997
ACM
81views Hardware» more  ISLPED 1997»
14 years 2 months ago
A method of redundant clocking detection and power reduction at RT level design
This paper proposes a novel method to estimate and to reduce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redundant clocki...
Mitsuhisa Ohnishi, Akihisa Yamada, Hiroaki Noda, T...
ICCAD
2003
IEEE
113views Hardware» more  ICCAD 2003»
14 years 6 months ago
Branch Merge Reduction of RLCM Networks
— In this paper we consider the problem of finding a smaller RLCM circuit that approximately replicates the behavior (up to a certain frequency) of a given RLCM circuit. Targeted...
Bernard N. Sheehan