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DATE
2000
IEEE
90views Hardware» more  DATE 2000»
14 years 2 months ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
14 years 1 months ago
A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
Xiao Liu, Qiang Xu
ISCAS
2007
IEEE
93views Hardware» more  ISCAS 2007»
14 years 4 months ago
VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding
Abstract— This paper describes the first VLSI implementation of lattice reduction (LR) aided multi-antenna broadcast precoding with vector perturbation. The considered LR scheme...
Andreas Burg, Dominik Seethaler, Gerald Matz
ICCAD
2006
IEEE
152views Hardware» more  ICCAD 2006»
14 years 6 months ago
Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression
Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models param...
Zhuo Feng, Peng Li
DAC
2008
ACM
13 years 11 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik