871 search results - page 38 / 175 » Streaming Reduction Circuit |
DDECS
2006
IEEE
14 years 4 months ago
2006
IEEE
- This paper presents a carry lookahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the p...
AVSS
2006
IEEE
14 years 4 months ago
2006
IEEE
This paper presents the implementation of a video segmentation unit used for embedded automated video surveillance systems. Various aspects of the underlying segmentation algorith...
DATE
2008
IEEE
14 years 4 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
GLVLSI
2010
IEEE
14 years 2 months ago
2010
IEEE
This paper presents a self-compensation scheme of manufacturing variability for clock skew reduction. In the proposed scheme, a CDN with embedded variability sensors tunes variabl...
ICCD
2002
IEEE
14 years 6 months ago
2002
IEEE
Power is considered to be the major limiter to the design of more faster and complex processors in the near future. In order to address this challenge, a combination of process, c...