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ISLPED
2004
ACM
169views Hardware» more  ISLPED 2004»
14 years 3 months ago
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
Deming Chen, Jason Cong
ISPD
2000
ACM
139views Hardware» more  ISPD 2000»
14 years 2 months ago
Critical area computation for missing material defects in VLSI circuits
We address the problem of computing critical area for missing material defects in a circuit layout. The extraction of critical area is the main computational problem in VLSI yield...
Evanthia Papadopoulou
ATS
1998
IEEE
76views Hardware» more  ATS 1998»
14 years 2 months ago
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits
We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: 1 fault-list and te...
Michael S. Hsiao, Srimat T. Chakradhar
GLVLSI
2009
IEEE
128views VLSI» more  GLVLSI 2009»
14 years 1 months ago
Impact of lithography-friendly circuit layout
Current lithography techniques use a light wavelength of 193nm to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual waf...
Pratik J. Shah, Jiang Hu
DAC
2008
ACM
14 years 11 months ago
On the role of timing masking in reliable logic circuit design
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes