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ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
15 years 20 days ago
Efficient power grid integrity analysis using on-the-fly error check and reduction
In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reductio...
Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai
ICCV
2009
IEEE
16 years 7 months ago
Dimensionality Reduction and Principal Surfaces via Kernel Map Manifolds
We present a manifold learning approach to dimensionality reduction that explicitly models the manifold as a mapping from low to high dimensional space. The manifold is represen...
Samuel Gerber, Tolga Tasdizen, Ross Whitaker
114
Voted
DATE
2009
IEEE
93views Hardware» more  DATE 2009»
15 years 9 months ago
Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing
Abstract—Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires ...
S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Ha...
113
Voted
CC
2007
Springer
126views System Software» more  CC 2007»
15 years 8 months ago
An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...
K. Shyam, R. Govindarajan
112
Voted
AMAST
2006
Springer
15 years 6 months ago
State Space Reduction of Rewrite Theories Using Invisible Transitions
Abstract. State space explosion is the hardest challenge to the effective application of model checking methods. We present a new technique for achieving drastic state space reduct...
Azadeh Farzan, José Meseguer