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» Subthreshold leakage modeling and reduction techniques
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ICCAD
2002
IEEE
144views Hardware» more  ICCAD 2002»
14 years 7 months ago
Subthreshold leakage modeling and reduction techniques
James Kao, Siva Narendra, Anantha Chandrakasan
DAC
2002
ACM
14 years 11 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
14 years 5 months ago
Microarchitecture floorplanning for sub-threshold leakage reduction
Lateral heat conduction between modules affects the temperature profile of a floorplan, affecting the leakage power of individual blocks which increasingly is becoming a larger ...
Hushrav Mogal, Kia Bazargan
DT
2007
57views more  DT 2007»
13 years 10 months ago
Leakage Minimization Technique for Nanoscale CMOS VLSI
This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage currents of nanometer CMOS circuits during sleep mode considering stack and fano...
Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Pa...
TIM
2010
294views Education» more  TIM 2010»
13 years 5 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi