37 search results - page 4 / 8 » Subthreshold leakage modeling and reduction techniques |
PATMOS
2004
Springer
14 years 4 months ago
2004
Springer
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as...
EUC
2004
Springer
14 years 4 months ago
2004
Springer
Abstract. Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltag...
VLSID
2006
IEEE
14 years 11 months ago
2006
IEEE
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
ICCD
2008
IEEE
14 years 7 months ago
2008
IEEE
— Run-time Active Leakage Reduction (RALR) is a recent technique and aims at aggressively reducing leakage power consumption. This paper studies the feasibility of RALR from the ...
ICCAD
2004
IEEE
14 years 7 months ago
2004
IEEE
In this paper, we propose a new technique for the combined voltage scaling of processors and communication links, taking into account dynamic as well as leakage power consumption....