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IPPS
2006
IEEE
14 years 1 months ago
Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...
Kostas Siozios, Konstantinos Tatas, Dimitrios Soud...
ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Compiler based exploration of DSP energy savings by SIMD operations
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
Markus Lorenz, Peter Marwedel, Thorsten Dräge...
DATE
1998
IEEE
153views Hardware» more  DATE 1998»
13 years 12 months ago
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
Jan M. Rabaey, Marlene Wan
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
14 years 2 months ago
A Virtual Prototype for Bluetooth over Ultra Wide Band System Level Design
The industry is merging two different Wireless Personal Area Networks (WPAN) technologies: Bluetooth (BT) and WiMedia Ultra Wide Band (UWB), into a single BT over UWB (BToUWB) spe...
Alexandre Lewicki, Javier del Prado Pavon, Jacky T...
ICPP
2002
IEEE
14 years 17 days ago
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha