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DAC
2004
ACM
14 years 9 months ago
A method for correcting the functionality of a wire-pipelined circuit
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
Vidyasagar Nookala, Sachin S. Sapatnekar
ASPDAC
1999
ACM
98views Hardware» more  ASPDAC 1999»
14 years 28 days ago
A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler
− In this paper, we propose a scheduling method for synchronous communication between threads in the Bach hardware compiler. In this method, all communications are extracted from...
Ryoji Sakurai, Mizuki Takahashi, Andrew Kay, Akihi...
ICCAD
1993
IEEE
111views Hardware» more  ICCAD 1993»
14 years 22 days ago
Unifying synchronous/asynchronous state machine synthesis
We present a design style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed design style not only supports generalized “bur...
Kenneth Y. Yun, David L. Dill
DAC
2004
ACM
14 years 2 months ago
Large-scale placement by grid-warping
Grid-warping is a new placement algorithm based on a strikingly simple idea: rather than move the gates to optimize their location, we elastically deform a model of the 2-0 chip s...
Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob ...
ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
14 years 1 months ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu