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ISLPED
2009
ACM
97views Hardware» more  ISLPED 2009»
14 years 3 months ago
A high-performance low-power nanophotonic on-chip network
On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfer, limits the...
Zheng Li, Jie Wu, Li Shang, Alan R. Mickelson, Man...
ASYNC
2007
IEEE
131views Hardware» more  ASYNC 2007»
14 years 3 months ago
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughpu...
Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia...
APCCAS
2006
IEEE
227views Hardware» more  APCCAS 2006»
14 years 2 months ago
FPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam Plane-wave Filters
— We propose a VLSI architecture for the single-chip realization of 2D spatio-temporal IIR digital filters, consisting of a meshed connection of concurrent identical vector-proce...
Arjuna Madanayake, Leonard T. Bruton
DFT
2006
IEEE
82views VLSI» more  DFT 2006»
14 years 2 months ago
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation
In this paper we will introduce a novel approach for the on-chip generation of a faulttolerant clock. We will motivate why it becomes more and more desirable to provide VLSI circu...
Markus Ferringer, Gottfried Fuchs, Andreas Steinin...
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
14 years 2 months ago
Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices
This paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmabl...
Sajid Baloch, Tughrul Arslan, Adrian Stoica