243 search results - page 40 / 49 » Synchronous Elastic Circuits |
FTEDA
2007
13 years 8 months ago
2007
The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks i...
ASPDAC
2010
ACM
13 years 6 months ago
2010
ACM
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
FPL
2010
Springer
13 years 6 months ago
2010
Springer
This paper presents a novel IP core reuse strategy which reduces design time from days to hours for communication circuits such as digital radio receivers. This design productivity...
DSN
2007
IEEE
14 years 2 months ago
2007
IEEE
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
We discuss the problem of Concurrent Error Detection (CED) in a popular class of asynchronous controllers, namely Burst-Mode machines. We first outline the particularities of the...