95 search results - page 5 / 19 » Synchronous Interlocked Pipelines |
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
ISLPED
2004
ACM
14 years 26 days ago
2004
ACM
This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a ...
VLSI
2010
Springer
13 years 5 months ago
2010
Springer
—Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elas...
ARVLSI
1999
IEEE
13 years 11 months ago
1999
IEEE
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
- In this paper, we present a technique to optimize the energy-delay product of a synchronous linear pipeline circuit with dynamic error detection and correction capability running...