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CODES
2009
IEEE
13 years 11 months ago
Building heterogeneous reconfigurable systems with a hardware microkernel
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a softwarelike ...
Jason Agron, David L. Andrews
ITC
1998
IEEE
61views Hardware» more  ITC 1998»
13 years 12 months ago
Test session oriented built-in self-testable data path synthesis
Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of large design spa...
Han Bin Kim, Takeshi Takahashi, Dong Sam Ha
ISSS
2002
IEEE
133views Hardware» more  ISSS 2002»
14 years 16 days ago
Efficient Simulation of Synthesis-Oriented System Level Designs
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu
DATE
2008
IEEE
156views Hardware» more  DATE 2008»
14 years 2 months ago
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications
Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in ...
Antonio Carlos Schneider Beck, Mateus B. Rutzig, G...
ASPDAC
2009
ACM
133views Hardware» more  ASPDAC 2009»
13 years 8 months ago
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor
Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations a...
Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiro...