68 search results - page 6 / 14 » Synthesis of Power Efficient Systems-on-Silicon |
IESS
2007
Springer
14 years 4 months ago
2007
Springer
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
CODES
2006
IEEE
14 years 3 months ago
2006
IEEE
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
DAC
2000
ACM
14 years 10 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
DAC
2003
ACM
14 years 10 months ago
2003
ACM
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
: In this paper, we present a point-to-point (P2P) communication synthesis methodology for SystemOn-Chip (SOC) design. We consider real-time systems where IP selection, mapping and...