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» Synthesis of Testable RTL Designs
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ICCAD
2009
IEEE
131views Hardware» more  ICCAD 2009»
13 years 8 months ago
Scheduling with soft constraints
In a behavioral synthesis system, a typical approach used to guide the scheduler is to impose hard constraints on the relative timing between operations considering performance, a...
Jason Cong, Bin Liu, Zhiru Zhang
DAC
2007
ACM
14 years 12 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
ASPDAC
2004
ACM
83views Hardware» more  ASPDAC 2004»
14 years 4 months ago
A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline
Much attention has been directed to different aspects of the design of pipelines [1,2,3,4]. Design of the control logic of non-linear pipelines has however, been considered as a su...
Hashem Hashemi Najaf-abadi
IOLTS
2008
IEEE
83views Hardware» more  IOLTS 2008»
14 years 5 months ago
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises s...
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, ...
ICCAD
2008
IEEE
246views Hardware» more  ICCAD 2008»
14 years 7 months ago
MC-Sim: an efficient simulation tool for MPSoC designs
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...
Jason Cong, Karthik Gururaj, Guoling Han, Adam Kap...