64 search results - page 6 / 13 » Synthesis of locally exhaustive test pattern generators |
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
3DPVT
2006
IEEE
13 years 9 months ago
2006
IEEE
3D scanning techniques based on structured light usually achieve robustness against outliers by performing multiple projections to simplify correspondence. However, for cases such...
ICCAD
2002
IEEE
14 years 13 days ago
2002
IEEE
The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is exp...
GLVLSI
2002
IEEE
14 years 13 days ago
2002
IEEE
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
ICRA
2010
IEEE
13 years 6 months ago
2010
IEEE
— Building upon previous work that demonstrates the effectiveness of WiFi localization information per se, in this paper we contribute a mobile robot that autonomously navigates ...