419 search results - page 2 / 84 » Synthesis of networks on chips for 3D systems on chips |
DAC
2011
ACM
12 years 7 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
NOCS
2009
IEEE
14 years 2 months ago
2009
IEEE
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
DFT
2005
IEEE
14 years 1 months ago
2005
IEEE
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...