419 search results - page 54 / 84 » Synthesis of networks on chips for 3D systems on chips |
ASPDAC
1995
ACM
14 years 6 days ago
1995
ACM
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
ISPAN
2005
IEEE
14 years 2 months ago
2005
IEEE
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
SAMOS
2005
Springer
14 years 2 months ago
2005
Springer
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chi...
GLVLSI
2009
IEEE
14 years 15 days ago
2009
IEEE
To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both ...