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» Synthesis of networks on chips for 3D systems on chips
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DFT
2004
IEEE
174views VLSI» more  DFT 2004»
14 years 9 days ago
Defect Avoidance in a 3-D Heterogeneous Sensor
A 3D Heterogeneous Sensor using a stacked chip is investigated. Optical Active Pixel Sensor and IR Bolometer detectors are combined to create a multispectral pixel for aligned col...
Glenn H. Chapman, Vijay K. Jain, Shekhar Bhansali
DAC
2010
ACM
14 years 14 days ago
Networks on Chips: from research to products
Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address th...
Giovanni De Micheli, Ciprian Seiculescu, Srinivasa...
SIGGRAPH
1993
ACM
14 years 19 days ago
Leo: a system for cost effective 3D shaded graphics
A physically compact, low cost, high performance 3D graphics accelerator is presented. It supports shaded rendering of triangles and antialiased lines into a double-buffered 24-bi...
Michael F. Deering, Scott R. Nelson
DAC
1998
ACM
14 years 9 months ago
A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects
As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate threedimensional interconnect models. In this paper, we describe...
Nuno Alexandre Marques, Mattan Kamon, Jacob White,...
DAC
2006
ACM
14 years 9 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...