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» System Exploration of SystemC Designs
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DAC
2006
ACM
14 years 3 months ago
SystemC transaction level models and RTL verification
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
Stuart Swan
ISCAS
2005
IEEE
166views Hardware» more  ISCAS 2005»
14 years 2 months ago
Extending SystemC to support mixed discrete-continuous system modeling and simulation
—Systems on chip are more and more heterogeneous and include software, analog/RF and digital hardware, and non-electronic components such as sensors or actuators. The design and ...
Alain Vachoux, Christoph Grimm, Karsten Einwich
EMSOFT
2005
Springer
14 years 2 months ago
Pinapa: an extraction tool for SystemC descriptions of systems-on-a-chip
SystemC is becoming a de-facto standard for the description of complex systems-on-a-chip. It enables system-level descriptions of SoCs: the same language is used for the descripti...
Matthieu Moy, Florence Maraninchi, Laurent Maillet...
DATE
2005
IEEE
155views Hardware» more  DATE 2005»
14 years 2 months ago
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC
This paper presents the methodology and the modeling constructs we have developed to capture the real time aspects of RTOS simulation models in a System Level Design Language (SLD...
M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori ...
DAC
2008
ACM
14 years 10 months ago
Predictive runtime verification of multi-processor SoCs in SystemC
Concurrent interaction of multi-processor systems result in errors which are difficult to find. Traditional simulationbased verification techniques remove the concurrency informat...
Alper Sen, Vinit Ogale, Magdy S. Abadir